In recent years, the performance of components configuring computers and information processing devices has been significantly improved. For example, the performance of static random access memories (SRAMs), dynamic random access memories (DRAMs), processors, switch LSIs, and so on has been improved. Accordingly, to improve the performance of the entire system, it is preferable to improve a signal transmission speed among these components or elements.
For example, a gap in speed between a memory such as an SRAM or DRAM and a processor tends to increase, and this speed gap is gradually hindering improvement in computer performance in recent years. Moreover, with an increase in chip size, not only the speed in signal transmission between these chips but also the speed in signal transmission between elements in a chip and between circuit blocks serves as a major factor in restricting chip performance. Furthermore, signal transmission between a peripheral device and a processor/chip set also serves as a factor in restricting the performance of the entire system.
To increase the speed in signal transmission between circuit blocks, between chips, or within a housing, it is important to propagate a high-speed clock to a circuit block without degrading the quality of the clock (such as skew or jitter amount), because clock timing accuracy provides reception timing accuracy and timing accuracy of a generated signal.
With this improvement in transmission rate, a current mode logic (CML) buffer is increasingly adopted to a clock transmission circuit, as typified by a high-speed serializer/deserializer (SerDes) in recent years. A reason for this is, for example, that the CML buffer has a jitter performance lower than that of a complementary metal oxide semiconductor (CMOS) buffer. The CML buffer is a type of clock transmission circuit for differential clock transmission. The CML buffer operates in a manner such that when one of input signals, which are paired differential signals, rises to a high level, the other is down to a low level, thereby making the balance of operation of the differential signals favorable.
In related art, current feedback is performed in the above-described CML buffer so that common voltages of an input signal and an output signal are equal to each other, thereby reducing jitters.
Here, in the CML buffer, the output amplitude may be decreased due to a shortage of bands of the single CML buffer, causing the CML buffer to become easily influenced by variability at the time of manufacturing and causing an occurrence of a difference between common voltages of an output of one of the paired differential signals and an output of the other in a transmission clock. In this case, a differential duty ratio may be out of balance. When the differential duty ratio is out of balance, it is difficult to generate an appropriate clock.
Furthermore, when CML buffers are connected in a multistage manner, one output and the other output are separated apart from each other every passage through each stage, possibly increasing the difference in common voltage therebetween.
To address this problem, in related art, a capacitive cell is disposed between CML buffers to cut a direct current (DC) component, thereby adjusting the difference in common voltage between differential signals.
However, to cut a DC component at a low frequency, a large capacitive cell is used. Therefore, to allow a clock transmission circuit to support a clock with a wide frequency band, a large-sized capacitive cell is used, thereby enlarging the mounting area of the clock transmission circuit.
The following is reference document:    [Document 1] Japanese Laid-open Patent Publication No. 2003-347920.